1. Field of the Invention
Example embodiments relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having an Outer Data Inner Control (ODIC) pad structure and a memory system including the same.
2. Description of the Related Art
A conventional semiconductor memory device having an ODIC pad structure has a structure in which data pads are disposed at both sides thereof and a command pad is disposed at an inner side thereof. Data input and output via the data pad disposed at one side may be input and output through only a memory cell array block disposed at one side, and data input and output via the data pad disposed at the other side may be input and output through only a memory cell array block disposed at the other side.
FIG. 1 is a block diagram of a conventional semiconductor memory device having an ODIC pad structure, which may include four memory cell array blocks BLK1 to BLK4, for example.
Referring to FIG. 1, a first group of data pads DQ1, address/command signal applying pads CMD/ADD and a second group of data pads DQ2 may be arranged in a line between a region where the memory cell array blocks BLK1 and BLK3 are disposed and a region where the memory cell array blocks BLK2 and BLK4 are disposed. As shown in FIG. 1, the semiconductor memory device having the ODIC pad structure may have a first group of data pads DQ1 and a second group of data pads DQ2 disposed at both sides thereof, and the address/command signal applying pads CMD/ADD disposed at the center thereof.
Referring to FIG. 1, data DO1 and DO2 input/output to/from the memory cell array blocks BLK1 and BLK2 may be input/output via the first group of data pads DQ1 and data DO3 and DO4 input/output to/from the memory cell array blocks BLK3 and BLK4 may be input/output via the second group of data pads DQ2.
Conventional semiconductor memory devices may transmit data and an error detection code added to the data during a data transmission. For this purpose, conventional semiconductor memory devices may be provided with an error detection code generator. An error detection code generator may generate error detection codes for data of all bits output from the memory cell array blocks BLK1 to BLK4. If data is selectively output from the memory cell array blocks BLK1 and BLK3 or the memory cell array blocks BLK2 and BLK4, the generator may generate an error detection code for the data DO1 and DO4 or the data DO2 and DO3, for example.
However, if the error detection code generator is disposed in a region A between regions where the blocks BLK1 to BLK4 are disposed and the data are output from the data DO1 and DO4 or the data DO2 and DO3, the data DO1 and DO4 or the data DO2 and DO3 should be input to the error detection code generator. Accordingly, signal lines for transmitting the data DO1 and DO2 and signal lines for transmitting the data DO3 and DO4 are generally disposed at the side of the error detection code generator. This not only increases the layout area of conventional semiconductor memory devices but also delays signal transmission due to increased length of the signal line or lines used to provide the data DO1, DO2, DO3 and DO4 to the error detection code generator.
Similar problems still in occur in conventional semiconductor memory devices even if the error detection code generator is disposed in a region B between regions where the memory cell array blocks BLK1 and BLK2 are disposed or in a region C between regions where the memory cell array blocks BLK3 and BLK4 are disposed.